Understanding ModelSim Simulation in VHDL, Verilog, and SystemC

ModelSim is a widely-used software tool for simulating hardware design languages such as VHDL, Verilog, and SystemC. This comprehensive guide delves into the core concepts of state models and evaluation steps involved in simulation to help you effectively design and debug your hardware descriptions.

State Models in Hardware Description Languages (HDLs)

In the realm of hardware description languages, the state of a model represents the current condition or value of the system being simulated. Understanding and managing these states are crucial for effective simulation. The common states in hardware descriptions are:

1 - High logic level 0 - Low logic level X - Unknown or indeterminate state Z - High impedance state U - Uninitialized state

These states are not only theoretical but form the backbone of how HDLs work and how they are interpreted by simulators like ModelSim.

Evaluation in ModelSim Simulation

The evaluation process in ModelSim is the procedure by which the state of a model is updated based on changes in the input or signal values. This process is triggered by changes in a sensitivity list, which includes signals that the model is sensitive to. When any of these signals change, ModelSim runs a simulation to produce the new state.

The general steps in the evaluation process include:

Sensitivity Update: The simulation engine checks for changes in the sensitivity list. Simulation Run: The model is executed to determine the new state based on the input changes. New State Creation: The simulation engine updates the model with the new state.

This recursive process continues until the simulation reaches a stable state or a pre-defined termination condition.

NAND Gates and Beyond: Simplistic and Complex Models

The simulation process can be as simple as evaluating a single NAND gate, where the inputs are directly controlled to produce a desired output, or as complex as simulating a complete SystemC design with intricate interactions between multiple components.

A NAND gate in VHDL, for example, would be defined as follows:

library IEEE;
use _LOGIC_;
entity nandgate is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           y : out  STD_LOGIC);
end nandgate;
architecture Behavioral of nandgate is
begin
    y  not(a and b);
end Behavioral;

Similarly, a basic SystemC module might be defined like this:

class nandGate
{
public:
    sc_inbool a, b;
    sc_outbool y;
    nandGate():
        a(nandInA), b(nandInB), y(nandOutY)
    {
        y  !(a  b);
    }
};

Both VHDL and SystemC have their own syntax and features, but they both ultimately follow the same basic principles of state models and evaluation.

Conclusion

ModelSim plays a pivotal role in the development and testing of hardware designs written in VHDL, Verilog, and SystemC. By understanding the fundamental concepts of state models and the evaluation process, you can effectively utilize ModelSim to simulate and validate your designs. Whether you are dealing with simple NAND gates or complex SystemC systems, the principles of state and evaluation remain consistent, allowing for a robust and reliable simulation environment.